The present invention relates to a method for forming a transistor of a memory device using a step Shallow Trench Isolation (STI) profile.
In general, a semiconductor memory device having a small cell size, such as a NAND flash memory device, has been used as a large-capacity storage of portable device. The NAND flash memory has been adapted to provide miniaturization and reduce the cost per bit while maintaining the characteristics of the memory device. The size of a transistor in the cell region and the peripheral region needs to be reduced to reduce the cost per bit for the NAND device. The reduction in cell size in the cell and peripheral regions, however, generally results in degradation of the performance of the corresponding transistors.
In a NAND flash memory of gigabit grade, the cell gate length of 0.1 μm or less is used and the peripheral transistor gate length of about 0.1-0.3 μm is used. The NAND device with such small or short channel experiences a variety of problems, including leakage current. For this reason, many people have attempted to solve the leakage current and other short channel effects using various methods such as the Pocket and Halo technique.
FIG. 1 shows a layout of a typical transistor. In FIG. 1, “M” indicates metal, “CT” indicates a contact and “FOX” indicates a region between active regions, or a field region. Furthermore, to reduce the overall chip size and to maintain good transistor characteristics in the cell and peripheral regions, a wide active region width (ACT) shown in FIG. 1 has been used. However, a unit transistor is vulnerable to leakage current because of the effects of an extremely short channel. Problems arise when a program state and an erase state of a cell are erroneously read, a circuit malfunctions and/or the standby current is increased since it becomes more difficult to provide sufficient current as the active area decreases. As a result, the performance of the transistor suffers as the channel size shrinks.
FIG. 2 shows a sectional view of a transistor that is generally used in order to compensate for the leakage current problem resulting from the reduction of the gate length (or the channel size), as described above. A gate 140 is formed on a semiconductor substrate 100. The leakage current is compensated by reducing the depletion width of the junction through ion implant. Gate spacers 150 are formed on the sidewalls of the gate 140.
This method compensates for the leakage current by providing pocket and halo implants 130 that are selectively injected into the ends of the junction to reduce the depletion width of the junction. In addition, shallow junctions 120 are formed to compensate for the problem of a deep junction 110. To reduce Rs (surface resistance) and Rc (contact resistance), methods such as forming an amorphous junction through implantation of Si and Ge have been used.
However, such a method is difficult to implement, and also it is difficult to uniformly obtain the desired characteristics for each unit transistor. Consequently, reducing the chip size while maintaining the desired transistor characteristics represent a difficult challenge for the semiconductor industry.